`timescale 1ns / 1ps

module MEM_WB(
    input clk,
    input reset,
    input [31:0] M_AO,
    input [31:0] M_DR,
    input [31:0] M_PC,
    input [2:0] M_RinSel,
    input M_RegWr,
    input [4:0] M_A1,
    input [4:0] M_A2,
    input [1:0] M_Tu1,
    input [1:0] M_Tu2,
    input [4:0] M_A3,
    input [1:0] M_Tn,
    input [2:0] M_Dop,
    input [31:0] M_MDV,
    input [31:0] M_instr,
    input [31:0] M_CP0_Dout,
    output reg [31:0] W_AO,
    output reg [31:0] W_DR,
    output reg [31:0] W_PC,
    output reg [2:0] W_RinSel,
    output reg W_RegWr,
    output reg [4:0] W_A1,
    output reg [4:0] W_A2,
    output reg [1:0] W_Tu1,
    output reg [1:0] W_Tu2,
    output reg [4:0] W_A3,
    output reg [1:0] W_Tn,
    output reg [2:0] W_Dop,
    output reg [31:0] W_MDV,
    output reg [31:0] W_instr,
    output reg [31:0] W_CP0_Dout
    );

    initial begin
    W_AO <= 0;
    W_DR <= 0;
    W_PC <= 0;
    W_RinSel <= 0;
    W_RegWr <= 0;
    W_A1 <= 0;
    W_A2 <= 0;
    W_Tu1 <= 0;
    W_Tu2 <= 0;
    W_A3 <= 0;
    W_Tn <= 0;
    W_Dop <= 0;
    W_MDV <= 0;
    W_CP0_Dout <= 0;
    end

always @(posedge clk) begin
    if(reset) begin
    W_AO <= 0;
    W_DR <= 0;
    W_PC <= 0;
    W_RinSel <= 0;
    W_RegWr <= 0;
    W_A1 <= 0;
    W_A2 <= 0;
    W_Tu1 <= 0;
    W_Tu2 <= 0;
    W_A3 <= 0;
    W_Tn <= 0;
    W_Dop <= 0;
    W_MDV <= 0;
    W_CP0_Dout <= 0;
    end
    else begin
    W_AO <= M_AO;
    W_DR <= M_DR;
    W_PC <= M_PC;
    W_RinSel <= M_RinSel;
    W_RegWr <= M_RegWr;
    W_A1 <= M_A1;
    W_A2 <= M_A2;
    W_Tu1 <= M_Tu1;
    W_Tu2 <= M_Tu2;
    W_A3 <= M_A3;
    W_Tn <= (M_Tn == 0)? 0 : (M_Tn - 1);  
    W_Dop <= M_Dop;
    W_MDV <= M_MDV;
    W_CP0_Dout <= M_CP0_Dout;
    end
end

endmodule
